1. Field of the Invention
The present invention relates to a method for fabricating an isolation layer in a semiconductor device, and more particularly to a method for fabricating an isolation layer in a semiconductor device which can improve the ability to fill fine patterns.
2. Description of the Prior Art
As generally known in the art, a width of an isolation insulating layer formed in a STI (Shallow Trench Isolation) process decreases with the advance of integration degree in a semiconductor device. Although the isolation insulating layer in the semiconductor device is formed according to a APCVD (Atmosphere Pressure Chemical Vapor Deposition) or a HDPCVD (High Density Plasma Chemical Vapor Deposition) process, limitations exist in their ability to fill fine patterns in a conventional isolation insulating layer as a width of a shallow trench decreases.
Further, in the case of a flowing SOD (Spin On Dielectric) insulating layer, although it is good in its ability to fill fine patterns, as the density of the filled insulating layer is so low as to result hi the loss of insulation due to loss of the insulating layer in the following etching and cleaning processes, and the insulation of the semiconductor device decreases due to permeation of ions into the STI insulating layer having a low density in the following ion implanting process.
A method for depositing fine insulating layer again after depositing the SOD insulating layer in order to solve the above problems has-been researched, however it has been impossible to make the insulating layer filled in more minute fine patterns because a thickness of the insulating layer deposited by means of the SOD insulating layer is bigger than the width of the fine patterns.
The above conventional method for fabricating an isolation layer by using the SOD insulating layer as a flowing insulating layer is described below with reference to FIG. 1 and FIG. 2.
As shown in FIG. 1, after a pad oxide film 13 and a pad nitride film 15 are stacked on a silicon substrate 11, a trench (not shown) is formed by performing excessive etching of the silicon substrate 11 together with these films by using a mask (not shown) for making a trench.
Then, a plasma treatment is performed with using a N2O or O2 plasma, before forming the SOD insulating layer 19.
Subsequently, the SOD insulating layer 19 is deposited in the trench (not shown), and then an insulating layer (not shown) for filling gaps is deposited on an upper surface of overall structure inclusive of the SOD insulating layer 19 in the following process, and the process for fabricating the isolation layer of the semiconductor device progresses continuously.
However, according to the prior art, in the case of forming a flowing insulating layer in a portion with narrow space at the time of fabricating highly integrated semiconductor device, as shown by “A” in FIG. 1 and FIG. 2, fine pores are produced beside the active regions at sides of the trench in particular when the flowing SOD insulating layer is deposited in the trench.
Further, although O2 plasma is used in place of N2O plasma in the case of performing plasma treatment as a pretreatment process before depositing the flowing insulating layer, the removal of the fine pore defects has not been considerably improved.